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yinuoli1114
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0409_Verilog_YinuoLi
6 labs and 1 project
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6 labs and 1 project
Languages
Language:
Verilog
42.1%
Language:
SystemVerilog
26.6%
Language:
JavaScript
16.4%
Language:
Makefile
7.8%
Language:
VHDL
3.2%
Language:
CSS
1.7%
Language:
Python
1.7%
Language:
Tcl
0.3%
Language:
Stata
0.2%
Language:
Io
0.1%