Pipelined processor is an updated version of single cycle processor
The Pipelined CPU supports 34 MIPS instructions, with its integer unit and floating-point unit handling integer and floating-point calculation respectively. The execution of each instruction is divided into 5 stages: Instruction Fetch, Instruction Decode, Execution, Memory Access, and Write Back, which can maximize the use of hardware resources. However, hazards come along with this design, thus, I also implemented the following hazard handling mechanism in this CPU: (1) the separation of data and instruction cache. (2) internal forwarding and pipeline pausing. (3) delay branch. I design a simple memory hierarchy for this CPU, when a cache miss happens, the pipeline pauses and the CPU has to access memory. When a TLB miss happens, the program counter jumps to the pre-set address of the exception handler. To simplify the implementation, my dual-core CPU does not realize cache coherence protocol and only has a one-layer cache. The CPU has a one-bit counter to specify the priority of core1 and core2 to accessing the memory. This project helped me better understand classic computer architecture and further sparked my interest in high-performance processor design.