yathAg

Yatharth Agarwal's repositories

800

Understanding Physical Verification using open source tools such as Magic and Netgen

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RTL to GDSII for RISC V Core with SRAM

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Codes for the shakti processor

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Power distribution system for 12S 30A Hex-Rotor propultion System

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RISCV32I single core processor with UART implemented on the ARTIX7 FPGA

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Learning FPGA, yosys, nextpnr, and RISC-V

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OpenROAD's scripts implementing an RTL-to-GDS Flow. Documentation at https://openroad-flow-scripts.readthedocs.io/en/latest/

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STM32 Nucleo Shields for CAN and RS485

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Smart ASRS Sytem Using Shakti RISCV Processor

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time library for shakti sdk

Language:CGPL-3.0000