Yannick Reiß's repositories

brainfuck_processor

Implementation of Brainfuck in VHDL and Verilog with compiler to generate matching machine code

Language:TclLicense:GPL-3.0Stargazers:0Issues:0Issues:0

c2bf

C2BF is a C compiler targeting brainfuck, written by the twisted mind of Gregor Richards.

Language:CStargazers:0Issues:0Issues:0
Language:TclStargazers:0Issues:1Issues:0
Language:TclStargazers:0Issues:0Issues:0
Language:CStargazers:0Issues:1Issues:0

IHP-Open-PDK

130nm BiCMOS Open Source PDK, dedicated for Analog, Mixed Signal and RF Design

Language:HTMLLicense:Apache-2.0Stargazers:0Issues:0Issues:0

InfinitumBotty

Copy for Botty

Language:PythonLicense:GPL-3.0Stargazers:0Issues:0Issues:0

lemoa

Native Gtk client for Lemmy

Language:RustLicense:GPL-3.0Stargazers:0Issues:0Issues:0
Language:RustLicense:MITStargazers:0Issues:1Issues:0

tt04-ripple-carry-adder

Tiny Tapeout 4 Ripple Carry Adder

Language:TclLicense:Apache-2.0Stargazers:0Issues:0Issues:0
Language:VerilogLicense:Apache-2.0Stargazers:0Issues:0Issues:0

mc6809

Cycle-Accurate MC6809/E implementation, Verilog, VHDL

Language:VerilogStargazers:0Issues:0Issues:0
Language:Vim SnippetStargazers:0Issues:1Issues:0
Language:Vim ScriptStargazers:0Issues:0Issues:0

PiFmRds

FM-RDS transmitter using the Raspberry Pi's PWM

Language:CLicense:GPL-3.0Stargazers:0Issues:0Issues:0
License:CC0-1.0Stargazers:0Issues:0Issues:0
License:Apache-2.0Stargazers:0Issues:0Issues:0
Language:VerilogLicense:Apache-2.0Stargazers:0Issues:1Issues:0
Language:VerilogLicense:Apache-2.0Stargazers:0Issues:0Issues:0
Language:VerilogLicense:Apache-2.0Stargazers:0Issues:0Issues:0
Language:TclLicense:Apache-2.0Stargazers:0Issues:0Issues:0
Language:VHDLLicense:Apache-2.0Stargazers:0Issues:1Issues:0
Language:TclLicense:Apache-2.0Stargazers:0Issues:0Issues:0
Language:VerilogLicense:Apache-2.0Stargazers:0Issues:0Issues:0

tt06-stack

Submission template for Tiny Tapeout 06 - Verilog HDL Projects

Language:VerilogLicense:Apache-2.0Stargazers:0Issues:0Issues:0
Language:VerilogLicense:Apache-2.0Stargazers:0Issues:1Issues:0
Language:TclLicense:Apache-2.0Stargazers:0Issues:0Issues:0
Language:TclLicense:Apache-2.0Stargazers:0Issues:1Issues:0
Language:VerilogLicense:Apache-2.0Stargazers:0Issues:1Issues:0

VexRiscv

A FPGA friendly 32 bit RISC-V CPU implementation

Language:AssemblyLicense:MITStargazers:0Issues:0Issues:0