xsld1

Vitis-In-Depth-Tutorial

Vitis-AI-DPU_TRD-for-ZCU106

Port of the ZCU104_dpu Vitis Platform to the ZCU106 with instructions to build Vitis DPU_TRD

Vitis_Embedded_Platform_Source

DPU-PYNQ

DPU on PYNQ

Face-Emotion-Recognition-On-FPGA

Vitis-AI

Vitis AI is Xilinx’s development stack for AI inference on Xilinx hardware platforms, including both edge devices and Alveo cards.

AccDNN

A compiler from AI model to RTL (Verilog) accelerator in FPGA hardware with auto design space exploration.

context_adaptive_neural_network_based_prediction

Context-adaptive neural network based prediction for image compression https://arxiv.org/abs/1807.06244

HEVC-Complexity-Reduction

Source programs to test the deep-learning-based complexity reduction approach for HEVC, at both intra- and inter-modes.

CPIH

A large-scale database for CTU partition of intra-mode HEVC (CPIH)

CPH

A large-scale database for CU partition of HEVC (CPH), at both intra- and inter-modes.

pytorch-handbook

pytorch handbook是一本开源的书籍，目标是帮助那些希望和使用PyTorch进行深度学习开发和研究的朋友快速入门，其中包含的Pytorch教程全部通过测试保证可以成功运行

intra_prediction

HEVC intra prediction based on impainting algorithm

CNN_Intra_Pred_Block

HEVC-deep-learning-pipeline

Integrating neural network models in HEVC encoder, to test the complexity reduction using deep learning in HEVC intra-prediction.

HEVC-CU-depths-dataset

A dataset that contains the Coding Unit image files and their corresponding depths for HEVC intra-prediction.