Icser's repositories
Attention-Based-Accelerator
Implement some hardware NN accelerators using spinalHDL
Brief-Chip
The Brief Chip is a Simple Soc project written in Spinal HDL , include a 3 stages RISCV CPU and a CNN Accelerator with RS Dataflow as Peripheral
HardWareHDL
Hardware HDL language about Spinal HDL and Chisel
Nvdla_Spinal
using the SpinalHDL to rebuild the NVDLA Arch
StylePatch
the source code of the StylePatch（a adversarial patch attack method using the local style fusion）
Awesome-Paper
The trace of Paper Reading about DSA、GPU、LLM and AI System
Multimodal-VLP
The Implement of MultiModal VLP Transformers Alg
RVGenerator
use to generate the random RISC-V instructions to test the CPU
awesome-tensor-compilers
A list of awesome compiler projects and papers for tensor computation and deep learning.
BitLLM
1.58 bit LLM
mysolution-xv6-labs-2020
A fork from git://g.csail.mit.edu/xv6-labs-2020 and provide my solution
NaxRiscv
super scala RISCV Core
Neural-Networks-on-Silicon
This is originally a collection of papers on neural network accelerators. Now it's more like my selection of research on deep learning and computer architecture.
OpenRPDK28
Open source process design kit for 28nm open process
PyRiscvCompiler
A compiler for RISCV implemented in pure Python
riscv-vector
Vector Acceleration IP core for RISC-V*
rocket-chip
Rocket Chip Generator
spatten-llm
[HPCA'21] SpAtten: Efficient Sparse Attention Architecture with Cascade Token and Head Pruning
SpinalHDL
Scala based HDL
tensil
Open source machine learning accelerators
tvm-vta
Open, Modular, Deep Learning Accelerator
tvm_mlir_learn
tvm learn