Yuehai Chen's repositories
ReckOn
ReckOn: A Spiking RNN Processor Enabling On-Chip Learning over Second-Long Timescales - HDL source code and documentation.
STBP-train-and-compression
STBP is a way to train SNN with datasets by Backward propagation.Using this Repositories allows you to train SNNS with STBP and quantize SNNS with QAT to deploy to neuromorphological chips like Loihi and Tianjic.
trng
True Random Number Generator core implemented in Verilog.
FPGA_SNN_STDP
FPGA acceleration of a Spike-Timing-Dependent Plasticity learning algorithm for Spiking Neural Networks
SpikingNeuralNet
Spiking neural network implementation using Verilog with LIF (Leaky Integrate-and-Fire) neurons
FPGA_Spiking_NN
CORDIC-SNN, followed with "Unsupervised learning of digital recognition using STDP" published in 2015, frontiers
XCryptCore
Implementation of cryptographic algorithm with verilog hdl(such as des,aes,sha,rsa,ecc etc.)
StepSTDP
StepSTDP is a new improved STDP algorithm for SNN training, which has good feasibility in hardware implementation
kamikaze
Light-weight RISC-V RV32IMC microcontroller core.
Fixed_weight_res_stdp
coop with gatech