wwei1988

System-Bus-Design-Verilog

This is a Multi master Multi slave compatible system bus design modeled using verilog. This is much like AMBA AHB Specification

apb2ic

APB to I2C converter Design & TB

clock_reset

verilog_everyday

the result of verilog everyday activity

apb_spi_master

Perl_OOP

Perl Package for better programming

forge

buggy_soc1

Buggy Pulpino SOC

Asynchronous-FIFO

Asynchronous fifo in verilog

320-Two-Phase-Handshake

Demonstration on the Two Phase Handshake in Verilog