Beast code in Giters

wt641496728's starred repositories

electron-python-example

Electron as GUI of Python Applications

Language:JavaScriptMIT2010 81 32

OpenLane

OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.

Language:PythonApache-2.01284 59 945

kianRiscV

RISC-V Linux SoC, marchID: 0x2b

Language:AGS ScriptISC649 28 4

ISP_UVM

A Framework for Design and Verification of Image Processing Applications using UVM

Language:SystemVerilogMIT86 90

pcievhost

PCIe (1.0a to 2.0) Virtual host model for verilog

Language:CGPL-3.072 12 4

A repository that compliments gpgpu-sim, providing automated regression scripts, simulation launching utilities and the code + arguments for simulations that complete in a reasonable amount of time on GPGPU-Sim.

Language:CudaBSD-2-Clause61 110

pcie-model

PCI Express controller model

Language:CNOASSERTION37 40

p1735_decryptor

IEEE P1735 decryptor for VHDL

Language:Python23 2 2

digital_ic_verification

数字IC验证案例（SV and UVM）

Language:SystemVerilog21 10

cybersecurity-digital-forensics

A collection of digital forensics tools for verification, investigations, diagnostics, software, libraries, learning tutorials, frameworks, academic and practical resources in Cybersecurity

Apache-2.019 30

Notes

Keep notes of all the courses I've taken

19 10

AHB-Lite-Protocol-Verification

Attempt to develop a verification IP and plan for a bus functional model of ARM based AMBA 3 AHB-LITE Protocol. Implemented object oriented programming techniques in SysteVerilog.

Language:SystemVerilogBSD-3-Clause16 10

tlm-of-a-pcie-rootcomplex-systemc

A transaction level model of a PCI express root complex implemented in systemc

Language:C++1500

PULP

A public repository discussing the PULP (Parallel Ultra Low Power) platform for open-source RISC-V processors and associated software.

900

Aurora

Automatic testbench and reference flow generation tool compatible with UVM and SVA.

Language:PythonMIT7 30

prune_uvmg

GUI based UVM Test Environment generation tool

Language:PythonMIT7 20

qm

Quality Management and QA/Verification plans and reports

Language:PerlApache-2.07 60

EN224-Test-et-verification

Digital design verification lesson provided at ENSEIRB-MATMECA school

Language:C++400

VHDL-DesignSynthesis

Design & Synthesis of several digital circuits in VHDL and Verilog. Scripting in TCL, simulation with Intel® ModelSim®, and synthesis under Synopsys® DC Ultra™.

Language:VerilogBSD-2-Clause4 10