wsuraiders67

DRFM

Code for paper entitled "Low Cost FPGA based Implementation of a DRFM System"

eudyptula

My take on the Eudyptula kernel programming Challenge, with subjects, walkthrough & tests. The Eudyptula Challenge was a series of programming exercises for the Linux kernel, that started from a very basic "Hello world" kernel module, moving on up in complexity to getting patches accepted into the main Linux kernel source tree.

flatpak-gnuradio-companion

A battery included Flatpak package for the GNURadio Companion

PoC

IP Core Library - Published and maintained by the Chair for VLSI Design, Diagnostics and Architecture, Faculty of Computer Science, Technische Universität Dresden, Germany

projf-explore

Project F brings FPGAs to life with exciting open-source designs you can build on.

C

Collection of various algorithms in mathematics, machine learning, computer science, physics, etc implemented in C for educational purposes.

SWE-agent

SWE-agent takes a GitHub issue and tries to automatically fix it, using GPT-4, or your LM of choice. It solves 12.47% of bugs in the SWE-bench evaluation set and takes just 1 minute to run.

radarsimpy

Radar Simulator built with Python and C++

docker-redhawk

Docker Images definitions and utility scripts for rapid development and deployment of REDHAWK SDR systems, Domains, and Devices.

Vitis-Tutorials

Vitis In-Depth Tutorials

gsrd-socfpga

linux

Linux kernel source tree

esp-idf

Espressif IoT Development Framework. Official development framework for Espressif SoCs.

professional-programming

A collection of learning resources for curious software engineers

vrtgen

100GBE-PYNQ

zynqmp-hailo-ai

Ref design combining the Zynq UltraScale+ MPSoC with the Hailo AI accelerator

FPGA-ASIC-Roadmap

A roadmap for those who want to build a career as an FPGA / ASIC Engineer

arm-trusted-firmware

Read-only mirror of Trusted Firmware-A

ghdl

VHDL 2008/93/87 simulator

vunit

VUnit is a unit testing framework for VHDL/SystemVerilog

en_cl_fix

Fixed-point math library with VHDL, Python and MATLAB support

verible

Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server

UnrolledBlockCiphers

canopen-stack

Free CANopen Stack for Embedded Systems

ZCU102-Ethernet

Ethernet Example Projects targeting the Xilinx ZCU102 evaluation board. This repository replaces XAPP1305.

psi_common

Common elements for FPGA Design (FIFOs, RAMs, etc.)

ideas

Random ideas and interesting ideas for things we hope to eventually do.

cpp_weekly

The official C++ Weekly Repository. Code samples and notes of future / past episodes will land here at various times. PR's will be accepted in some cases.

arm-trusted-firmware

ARM Trusted Firmware