This repository contains an implementation of a Clock agent, which is used for testbench clock generation, written in UVM 1.1d and SystemVerilog-2012.
Also, a complete user guide with the agent description, instructions and usage, is provided (TBD).
The main features of the Clock agent are:
- generating up to 32 unique clock sources
- run-time changing of each clock phase and period
- starting/stoping individual clock sources
- changing each clocks polarity value