wfjm / w11

PDP-11/70 CPU core and SoC

https://wfjm.github.io/home/w11/

wfjm/w11 Issues

A
Updated a year ago
DEUNA: buffer chaining not implemened in backend
Updated 2 years ago1
DZ11: modem control not implemented in backend
Updated 2 years ago
I have an ARTY S7 board, I'd like to try your w11 code.
Closed 2 years ago10
add external ram support on basys3 Implementation
Closed 2 years ago3
PSW changed after MMU aborts in dstw flows
Closed 2 years ago
CPU: no mmu trap when instruction which clears trap enable itself causes a trap
Closed 2 years ago1
CPU: several deficits in trap logic
Closed 2 years ago2
MMU trap delayed/lost when prefetch in s_idecode done
Closed 2 years ago1
MMU: D space used instead of I space for PC deferred specifiers
Closed 2 years ago
CPU: The AIB bit in MMU PDR register set independant of ACF field
Closed 2 years ago
MMU: PDR A bit is set for every access
Closed 2 years ago
MMU: ACF=1 traps on any access
Closed 2 years ago
CPU: MMR0 trap bit set when access aborted
Closed 2 years ago
CPU: src+dst deltas summed in mmr1 if register identical
Closed 2 years ago
asm-11 compiles nnn(pc) as nnn
Closed 2 years ago
SimH scmd files fail on current 4.* version; only 3.* supported
Closed 2 years ago5
Vivado xelab sometimes extremely slow
Closed 2 years ago1
dmscnt and dmcmon disabled in Vivado based flows
Closed 7 years ago3
time tbrun does not report correct CPU time
Updated 2 years ago
migrate from Travis to GitHub actions
Closed 2 years ago2
Help wanted: Testing with Arty S7 appreciated
Closed 2 years ago2
Help wanted: Testing with Nexys4 DDR (or Nexys A7-100T) appreciated
Closed 5 years ago1
fx2 interface blocks for certain workloads
Closed 7 years ago1
TM11 controller doesn't support odd transfer size
Closed 5 years ago1
w11 clock rate limited by CACHE-to-CACHE false path
Updated 5 years ago1
SEGFAULT core dump after detach; ReventLoop::RemovePollHandler() can cause race condition
Closed 5 years ago1
DL11: output chars lost when device polling used
Closed 5 years ago1
Bad throughput for DL11 emulation for low speed links
Closed 5 years ago1
RK11: write protect action too slow
Updated 5 years ago
How to understand tb log
Closed 6 years ago3
RK11,RL11: no proper NXM check in 18bit systems
Updated 6 years ago
rlink command lists aren't split to fit in retransmit buffer size
Updated 6 years ago
rlink v4 error recovery not yet implemented, will crash on error
Updated 6 years ago
IO delays still unconstraint in Vivado
Updated 6 years ago
Some exotic RH70/RP/RM features not implemented
Updated 6 years ago
tcl getters accessing a const reference crash with a SIGSEGV
Closed 6 years ago1
How to run testbench
Closed 6 years ago1
Designs fail to build under Vivado 2016.3 and 2016.4
Closed 8 years ago1
Many post-synthesis simulations fail
Updated 8 years ago
ti_rri crashes in normal rundown in very rare cases
Updated 8 years ago
rlink throughput on basys3/nexys4 limited by serial port stack round trip times
Updated 8 years ago