wangyipengw1p's repositories

ARM-Moniter-Debugger

course lab for Embedded System Design 北航嵌入式系统设计ARM大作业

Language:AssemblyLicense:MITStargazers:1Issues:0Issues:0

DAC-SDC-2019

Description and tools for DAC SDC 2019

Language:CStargazers:1Issues:0Issues:0

BUAAthesis

北航毕设论文LaTeX模板

Language:TeXLicense:NOASSERTIONStargazers:0Issues:0Issues:0

caj2pdf-actions

CAJ云转换,基于Github Actions

Language:PythonLicense:NOASSERTIONStargazers:0Issues:0Issues:0

darknet

Convolutional Neural Networks

Language:CLicense:NOASSERTIONStargazers:0Issues:0Issues:0
Language:SystemVerilogStargazers:0Issues:0Issues:0

Verilog-SystemVerilog-Xamples

A collection of useful modules for Verilog and Systemverilog

Language:SystemVerilogStargazers:0Issues:0Issues:0

VHDL-Xamples

Useful entities, docs and web page collection for VHDL

Language:VHDLLicense:GPL-3.0Stargazers:0Issues:0Issues:0

VHDL-Xgen

VHDL generation automation tool

Language:PythonLicense:MITStargazers:0Issues:0Issues:0

zynq

Practice projects for zynq

Language:HTMLStargazers:0Issues:0Issues:0

hexo-theme-next

Elegant and powerful theme for Hexo.

License:NOASSERTIONStargazers:0Issues:0Issues:0

ibex

Forked for UTRV

License:Apache-2.0Stargazers:0Issues:0Issues:0
Language:MatlabStargazers:0Issues:0Issues:0
Language:VerilogStargazers:0Issues:0Issues:0
Language:VHDLStargazers:0Issues:0Issues:0

riscv-isa-sim

Spike, a RISC-V ISA Simulator

Language:CLicense:NOASSERTIONStargazers:0Issues:0Issues:0

riscv_vhdl

(Learning) VHDL implementation of the RISC-V System-on-Chip based on bare "Rocket Chip".

Language:VerilogLicense:Apache-2.0Stargazers:0Issues:0Issues:0

ShuffleNet_V2_pytorch_caffe

ShuffleNet-V2 for both PyTorch and Caffe.

Language:PythonLicense:BSD-2-ClauseStargazers:0Issues:0Issues:0

Smartcar-humidifier-Arduino

Smart mobile small car / mobile humidifier, based on Arduino, with GUI in matlab

Language:C++Stargazers:0Issues:0Issues:0
Language:CSSStargazers:0Issues:0Issues:0