wangyenjen / CA2019-risc-v-cpu

A Verilog implementation of a RISC-V CPU, supporting RV32IM instruction set with cache & memory module

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A Verilog implementation of a RISC-V CPU, supporting RV32IM instruction set with cache & memory module

Language:Verilog 89.4%Language:C++ 6.7%Language:Shell 2.5%Language:Makefile 0.9%Language:Coq 0.5%