wangqueping's repositories
cores
Various HDL (Verilog) IP Cores
Cores-SweRV
SweRV EH1 core
corundum
Open source FPGA-based NIC and platform for in-network compute
ECCV2020-Code
ECCV 2020 论文开源项目合集,同时欢迎各位大佬提交issue,分享ECCV 2020开源项目
embeddedsw
Xilinx Embedded Software (embeddedsw) Development
FingerText
Tab triggered snippet plugin for Notepad++.
FPGAmp
720p FPGA Media Player (RISC-V + Motion JPEG + SD + HDMI on an Artix 7)
linux_kernel_wiki
linux内核学习资料:200+经典内核文章,100+内核论文,50+内核项目,500+内核面试题,80+内核视频
litepcie
Small footprint and configurable PCIe core
litesata
Small footprint and configurable SATA core
nmigen
A refreshed Python toolbox for building complex digital hardware
notepadqq
A simple, general-purpose editor for Linux
openISP
Image Signal Processor
phywhispererusb
PhyWhisperer-USB: Hardware USB Trigger
PYNQ
Python Productivity for ZYNQ
pyusb
USB access for Python
riscv-debug-spec
Working Draft of the RISC-V Debug Specification Standard
rocket-chip
Rocket Chip Generator
SpinalHDL
Scala based HDL
SpinalTemplateSbt
A basic SpinalHDL project
steel-core
Steel is a microprocessor core that implements the RV32I and Zicsr instruction sets of the RISC-V specifications.
TencentOS-tiny
腾讯物联网终端操作系统
UsbAsp-flash
Альтернативная прошивка и программа для UsbAsp, CH341a, AVRISP-MK2(LUFA) позволяющая программировать флеш память
verilator
Verilator open-source SystemVerilog simulator and lint system
verilog-pcie
Verilog PCI express components
VexRiscv
A FPGA friendly 32 bit RISC-V CPU implementation
vivado-build-system
Vivado build system