wangqueping's repositories
corundum
Open source FPGA-based NIC and platform for in-network compute
openISP
Image Signal Processor
linux_kernel_wiki
linux内核学习资料：200+经典内核文章，100+内核论文，50+内核项目，500+内核面试题，80+内核视频
vivado-build-system
Vivado build system
nmigen
A refreshed Python toolbox for building complex digital hardware
embeddedsw
Xilinx Embedded Software (embeddedsw) Development
pyusb
USB access for Python
notepadqq
A simple, general-purpose editor for Linux
verilator
Verilator open-source SystemVerilog simulator and lint system
phywhispererusb
PhyWhisperer-USB: Hardware USB Trigger
rocket-chip
Rocket Chip Generator
riscv-debug-spec
Working Draft of the RISC-V Debug Specification Standard
SpinalHDL
Scala based HDL
VexRiscv
A FPGA friendly 32 bit RISC-V CPU implementation
TencentOS-tiny
腾讯物联网终端操作系统
UsbAsp-flash
Альтернативная прошивка и программа для UsbAsp, CH341a, AVRISP-MK2(LUFA) позволяющая программировать флеш память
ECCV2020-Code
ECCV 2020 论文开源项目合集，同时欢迎各位大佬提交issue，分享ECCV 2020开源项目
cores
Various HDL (Verilog) IP Cores
litepcie
Small footprint and configurable PCIe core
PYNQ
Python Productivity for ZYNQ
litesata
Small footprint and configurable SATA core
Cores-SweRV
SweRV EH1 core
FPGAmp
720p FPGA Media Player (RISC-V + Motion JPEG + SD + HDMI on an Artix 7)
verilog-pcie
Verilog PCI express components
FingerText
Tab triggered snippet plugin for Notepad++.
steel-core
Steel is a microprocessor core that implements the RV32I and Zicsr instruction sets of the RISC-V specifications.
SpinalTemplateSbt
A basic SpinalHDL project