Vinay Singh's repositories
MasterThesis
repo contains code for Framework for Automatic Generation of Assertion
VerilogCodes
A repository of verilog codes of various digital circuits.
algorithmic-trading-python
The repository for freeCodeCamp's YouTube course, Algorithmic Trading in Python
goossens-book-ip-projects
this repository contains all the ip projects presented in the HLS/RISC-V/Computer Architecture book written by Goossens and published by Springer
Pyverilog
Python-based Hardware Design Processing Toolkit for Verilog HDL
MSOC1_code_repo
Code for assignments - EITF 35
CNN_for_SLR
A trained Convolutional Neural Network implemented on ZedBoard Zynq-7000 FPGA.
nvdl
RTL, Cmodel, and testbench for NVDLA
uvmprimer
Contains the code examples from The UVM Primer Book sorted by chapters.
Digital-Signal-Processing-Education-Kit
Digital Signal Processing Education Kit
Masimulator
Visual RISC-V Simulator
MIPS-Processor
5-stage pipelined 32-bit MIPS microprocessor in Verilog