Vinay Singh (vnay01)

vnay01

Geek Repo

Location:Helsingborg, Sweden

Home Page:https://www.linkedin.com/in/vnay01

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Vinay Singh's repositories

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MasterThesis

repo contains code for Framework for Automatic Generation of Assertion

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VerilogCodes

A repository of verilog codes of various digital circuits.

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algorithmic-trading-python

The repository for freeCodeCamp's YouTube course, Algorithmic Trading in Python

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goossens-book-ip-projects

this repository contains all the ip projects presented in the HLS/RISC-V/Computer Architecture book written by Goossens and published by Springer

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Pyverilog

Python-based Hardware Design Processing Toolkit for Verilog HDL

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MSOC1_code_repo

Code for assignments - EITF 35

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CNN_for_SLR

A trained Convolutional Neural Network implemented on ZedBoard Zynq-7000 FPGA.

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nvdl

RTL, Cmodel, and testbench for NVDLA

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uvmprimer

Contains the code examples from The UVM Primer Book sorted by chapters.

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Digital-Signal-Processing-Education-Kit

Digital Signal Processing Education Kit

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Masimulator

Visual RISC-V Simulator

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MIPS-Processor

5-stage pipelined 32-bit MIPS microprocessor in Verilog

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