vjkr / OpenLaneTools

Documenting individual open lane tools

openlane architecture and tools

OpenLaneTools

Documenting individual open lane tools This repository is a continuation from another repo where OpenLane is used for running inverter The purpose is to learn the maximum possible parts of OpenLane

Initializing the OpenLane

1. Open Terminal on Desktop
2. In this case, browse to make file which is provided by VSDFLOW cd /home/vijaykumar/Desktop/openlane/vsdflow/openlane_working_dir/OpenLane
3. check the setup by running make mount followed by ./flow.tcl -design spm
4. The flow should be complete without any errors.

Learning Synthesis using Yosys

1. Referring to this URL to understand the intricacies of Yosys - Synthesis
2. It seems we do not compulsorily need config.json file for synthesis. This can be inferred from steps 3 and 4. We will analyze the synthesized files with and without config.json.
3. Yosys can be invoked in openlane by typing yosys. Browse to directory containing verilog file /openlane/designs/inverter_testing2/src then run yosys

4. run steps read_verilog inverter.v followed by proc then opt ending with write_verilog synth.v

Exit yosys and analyze synth.v file

Analysing : This did not make sense. I will keep this for future.

6. Check with json file, whether there is any differnece. It is evident that yosys has generated exact same files for both the conditions. Hence config.json is not related to yosys. Care should be taken that yosys maybe different than synthesis part in Openlane.
7. Next we will analyze by writing different modelling style. Following is the conclusion

Somehow we ended with same synthesis! I had forgot techmap step. But putting techmap part didnt make any difference I will keep this pending for now.

Learning Synthesis in OpenLane

1. I ran ./flow.tcl -design spm -from synthesis -to synthesis without config.json file. I got an error!

2. After adding config.json, flow completes with results in /openlane/designs/inverter3/runs/RUN_2023.07.11_10.41.45/results/synthesis

4. There are two files .sdf and .v as below. these are interesting and are to be understood.

.sdf is standard delay format and .v is the synthesis file. the types of standard cells used from skywater can be read at naming

5. Let us try editing of config.json file diode_insertion_strategy is a mandatory requirement for flow to start. With only this prompt, STA fails with

   

   Adding clock_port , i.e total 4 prompts in config, the flow completes. The run results are same in terms of sdf and v files!! Same with changing diode insertion strategy from 3 to 1. LEF files are generated in tmp folder. I will check these in future study.

   Floorplanning

   There is no tool name for performing this other than 'Floor Planning: init_fp, ioPlacer, pdn and tapcell' as mentioned in readthedocs

6. The floorplan folder is empty as of now.

7. without proper config file following error occurs.

   

8. Too many errors were encountered , hence skipped to running ./flow.tcl -design inverter3 -from synthesis -to floorplan

   

9. All folders are empty, seems only planning is done. Results/reports are unavialble. i checked log files which are mentioned in above figure. Interesting data are there!!! Endcaps, tie cells, PDN, BUMP Pitches etc................. Let us study these later.

   

Placement

1. ./flow.tcl -design inverter3 -from synthesis -to placement generates

2. After running placement, results folder for floorplan contains 2 files, def file and odb file. let us study later.

3. BAck to placement. Four files as seen in below figure are seen in the results of placement. def files is more detailed version of def file in floorplan. nl.v file seems like a netlist file.

   

pnl.v seems like power netlist file. As it includes power lines too.

4. Some logs observed are cat designs/inverter3/runs/RUN_2023.07.12_11.04.39/logs/placement/7-global.log gives

cat designs/inverter3/runs/RUN_2023.07.12_11.04.39/logs/placement/8-resizer.log gives slack reports for everythig, setup, hold etc etc

designs/inverter3/runs/RUN_2023.07.12_11.04.39/logs/placement/9-detailed.log

CLOCK TREE SYNTHESIS CTS

1. ./flow.tcl -design inverter3 -from synthesis -to cts doesnot provide any results on terminal :(

2. No files in results too. Fortunately few reports are available as seen in below figure.

   

3. Very similar reports were seen during placement. Not sure what to make of these.

   Routing

   1. Verified that routing folder under results is empty. run ./flow.tcl -design inverter3 -from synthesis -to routing

   2. Many reports are generated and few are in results of routing.

      

4. Went through all reports. too many things are in process!. Let us keep this for research.

5. Studied all files under results. Again interesting. Let us compare all def files using magic!!

Tapeout

1. too many things in tapeout! Postpone study! ./flow.tcl -design inverter3 -from synthesis -to tapeout

Signoff

./flow.tcl -design inverter3 -from synthesis -to signoff

1. too many things in signoff! Postpone study! ./flow.tcl -design inverter3 -from synthesis -to signoff

2. Various files in the final folder. Let us study in detail

   

LET US STUDY ALL DEF FORMATS AT VARIOUS STEPS in next repo!