https://learning.edx.org/course/course-v1:LinuxFoundationX+LFD111x+3T2022/home
Building a RISC-V CPU Core (LFD111x) has been created by the Linux Foundation and RISC-V International in partnership with the Open Source FPGA Foundation.This is a crash course in digital logic design and basic CPU microarchitecture. Using the Makerchip
https://github.com/stevehoover/LF-Building-a-RISC-V-CPU-Core For latest updates on the course.
Launch Makerchip.com IDE
Open 'Long Division' example and split window to give space for 'log' window to observe results.Similarly for 'waveform' and 'logic'
Trying to complete first Lab by\
- Open the "Validity Tutorial".\
- Click "Load Pythagorean Example".\
- Split panes and move tabs between panes.\
- Zoom/pan in Diagram with the mouse wheel and drag.\
- Zoom Waveform with the "Zoom In" button.\
- Click $bb_sq to highlight. \
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Understand the TL-Verilog language syntax for expressing combinational and arithmetic logic functions.\
use of Visual Debug capabilities, unique to the Makerchip platform.\
Let’s try coding an inverter (a NOT gate) in Makerchip. As you go through this lab exercise, check the box for each step when done, to ensure you perform all required steps.
- Reload the Makerchip IDE to begin with the default code template. (You could also use Ctrl-Z in the Editor to restore to the default template or load the default template from the Examples page.)
- The first line of the source file specifies the TL-Verilog language version. If it is other than "1d", it may be necessary to revert the language version to be consistent with this course. In this case, check the GitHub repository for guidance.
- In place of "//...", type "$out = ! $in1;". Be sure to preserve the 3-spaces of indentation, similar to the surrounding expressions. This is an inverter.
- Compile and simulate (under the Editor’s "E" menu, or Ctrl-Enter). If any red X’s appear on the tabs (vs. green checkmarks), make sure you followed the instructions properly and try to resolve the issue. Use the LOG to debug if necessary, or use the video on the next page in times of desperation.\
1d on first line of code specifies TV-Verilog Language
In place of "//...", type "$out = ! $in1;"
TL-Verilog, your assignment statement acts as the declaration of its output signal(s)
There was no need to write a test bench to provide stimulus (input) to your inverter. Makerchip provides random stimulus for dangling inputs.
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Indentation
In TL-Verilog (within \TLV code blocks), indentation and whitespace are meaningful. Tabs (which have no consistently-defined behavior) are not permitted. Each level of indentation is 3 spaces (and the Makerchip editor helps with this).\
Signal Names
As long as you stick with the suggested signal names throughout this course, you won’t have any trouble, but, for those who might wish to veer off from the script a bit, TL-Verilog is picky about signal names too.
Implemented basic gates and full adder
Learnig arithmetic operations using an example of Parallel adder (implemented using + expression)
Verilog provides no less than six reasonable syntaxes for coding a multiplexer, each with pros and cons. TL-Verilog favors the use of the ternary (? :) operator, and we will stick with this throughout the course.
I am unable to implement calculator using ternary operator, keeping this for future work
limiting values on val1 and val2 which will help in analyzing the waveforms easily.I could not do this because of calculator hence did on parallel adder
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I am able to generate viz but not exact results. As i am using viz library for calculator but my code is parallel adder
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Also noteworthy is the fact that TL-Verilog is really a Verilog implementation of TL-X, a language extension defined to layer atop any HDL to extend it with transaction-level features. So there is a migration path from any supported HDL (and, as of this writing, Verilog is the only one).
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\in TLV, >>1 and >>2 implement previous version and pre-previous versions with the help of FFs
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A simple counter implementation can be done using following code
$num[31:0] = $reset ? 1 : (>>1$num + >>2$num);
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Use similar logic to connect output value of calculator (I have done for parallel adder) to input, and reset value when reset is asserted.
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By the end of this chapter, you should understand:
- The role of compilers and assemblers.
- The role of an instruction set architecture (ISA).
- The general properties of RISC-V versus other ISAs.
\Likely, you have experience writing programs in languages like Python, JavaScript, Java, C++, etc. These languages are portable and can run on just about any CPU hardware. CPU’s do not execute these languages directly. They execute raw machine instructions that have been encoded into bits as defined by an instruction set architecture (ISA). Popular ISAs include x86, ARM, MIPS, RISC-V, etc.
A compiler does the job of translating a program’s source code into a binary file or executable containing machine instructions for a particular ISA.The binary file is easily interpreted by hardware, but not so easily by a human. The ISA defines a human-readable form of every instruction, as well as the mapping of those human-readable assembly instructions into bits.
You will use assembly-level test programs in this course to debug your RISC-V design.
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\In this course, you will build a simple CPU that supports the RISC-V ISA. RISC-V has very rapidly gained popularity due to its open nature--its explicit lack of patent protection and its community focus. Following the lead of RISC-V, MIPS and PowerPC have subsequently gone open as well.
RISC-V is also popular for its simplicity and extensibility, which makes it a great choice for this course. "RISC", in fact, stands for "reduced instruction set computing" and contrasts with "complex instruction set computing" (CISC). RISC-V (pronounced "risk five") is the fifth in a series of RISC ISAs from UC Berkeley. You will implement the core instructions of the base RISC-V instruction set (RV32I), which contains just 47 instructions. Of these, you will implement 31 (Of the remaining 16, 10 have to do with the surrounding system, and 6 provide support for storing and loading small values to and from memory).\
Like other RISC (and even CISC) ISAs, RISC-V is a load-store architecture. It contains a register file capable of storing up to 32 values (well, actually 31). Most instructions read from and write back to the register file. Load and store instructions transfer values between memory and the register file.
All instructions are 32 bits. The R-type encoding provides a general layout of the instruction fields used by all instruction types. R-type instructions have no immediate value. Other instruction types use a subset of the R-type fields and provide an immediate value in the remaining bits.
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ONE OFTHE BEST VIDEOS EVER\
https://www.youtube.com/watch?v=6Rxade2nEjk
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In this chapter, you will build a subset of your RISC-V CPU core capable of executing a test program that adds numbers from 1 to 9. Subsequently, you will complete the functionality of your core.
By the end of this chapter, you should be able to:
- Explain the role of the fundamental components of a basic CPU microarchitecture.
- Be experienced in expressing digital logic using TL-Verilog.
- Develop an appreciation for the debug process within Makerchip, including: the interpretation of messages in the logs use of visual debug to understand the overall behavior of your logic, use of the waveform viewer to understand detailed behavior, tracing faulty behavior from symptom to cause
- Instantiate pre-existing Verilog and TL-Verilog components.
\The program we will execute on the CPU core is
\Open the makerchip starting point program from Steve's github repo
\Reference solutioons which are hidden
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Showcasing Your Work
git clone https://github.com/stevehoover/LF-Building-a-RISC-V-CPU-Core.git(and enter your credentials)
Then install the Makerchip app:
pip3 install makerchip-app
Installing makerchip on desktop and launching
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Within several hours, you will construct a CPU core that could be appropriate as a microcontroller. In contrast, a desktop or server CPU chip might be built by a team of hundreds of seasoned engineers over a period of several years.Our CPU will fully execute one instruction with each new clock cycle. Doing all of this work within a single clock cycle is only possible if the clock is running relatively slowly, which is our assumption.
We will start by implementing enough of the CPU to execute our test program. As you add each new piece of functionality, you will see in the VIZ pane the behavior you implemented, with more and more of the test program executing correctly until it is successfully summing numbers from one to nine. Then we will go back to implement support for the bulk of the RV32I instruction set.
In this course, we are focused on the CPU core only. We are ignoring all of the logic that would be necessary to interface with the surrounding system, such as input/output (I/O) controllers, interrupt logic, system timers, etc.It is typical to implement separate, single-cycle instruction and data caches, and our IMem and DMem are not unlike such caches.\
I could recreate the diagram and waveforms from reference solutions. Somehow I was expected to mention array size explicitly for 2nd line of code. + adding 4 is an important part of this design. Else PC will not be able to jump to next instruction.
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Instantiate verilog macro
`READONLY_MEM($addr, $$read_data[31:0])
\Typically, a memory structure like our IMem would be implemented using a physical structure called static random access memory, or SRAM. The address would be provided in one clock cycle, and the data would be read out in the next cycle. Our entire CPU, however, will execute within a single clock cycle. Our array provides its output data on the same clock cycle as the input address. Our macro would result in an implementation using flip-flops that would be far less optimal than SRAM.
Thanks to time spent on PC logic, I could implement IM easily
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Before we can interpret the instruction, we must know its type. This is determined by its opcode, in $instr[6:0]. In fact, $instr[1:0] must be 2'b11 for valid RV32I instructions. We will assume all instructions to be valid, so we can simply ignore these two bits. The ISA defines the instruction type to be determined as follows.
Unfortunately I could not write comparison operation in verilog, but did OR operation and implemented Instruction decode
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Now, based on the instruction type, we can extract the instruction fields. Most fields always come from the same bits regardless of the instruction type but only have meaning for certain instruction types. The imm field, an "immediate" value embedded in the instruction itself, is the exception. It is constructed from different bits depending on the instruction type.
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Modify the appropriate RF macro arguments to connect the decode output signals to the register file read input signals to read the correct registers when they are needed. Connect the output read data to new signals named $src1_value and $src2_value by replacing the appropriate macro arguments with these new signal names. (Bit ranges are not needed, as they are explicit within the macro definition.)
What does RD mean in RISC-V?
rs1 (5 bits) and rs2 (5 bits): Specify, by index, the first and second operand registers respectively (i.e., source registers). rd (5 bits): Specifies, by index, the destination register to which the computation result will be directed.
Something doesnot seem write at x12, But let us continue
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At this point, we are only going to implement support for the instructions in our test program. Since branch instructions do not produce a result value, we only need to support ADDI (which adds the immediate value to source register 1) and ADD (which adds the two source register values).
Still not right I guess, problem with x12
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$result needs to be written back to the destination register (rd) in the register file (if the instruction has a destination register).
After connecting result signal to RF, X12 problem has vanished.
The last piece of the puzzle to get your test program executing properly is to implement the branch instructions. Our test program uses BLT to repeat the loop body if the next incrementing value to accumulate is less than ten. And it uses BGE to loop indefinitely at the end of the test program. We’ll go ahead and implement all the conditional branch instructions now.
A conditional branch instruction will branch to a target PC if its condition is true. Conditions are a comparison of the two source register values. Implementing conditional branch instructions will require:
- Determining whether the instruction is a branch that is taken ($taken_br).
- Computing the branch target ($br_tgt_pc).
- Updating the PC ($pc) accordingly.
iMPLEMENTING Branch logic is confusing. I will keep it for future work.
rEPLACE EARLIER program with simple
m4_test_prog()
<img width="960" alt="image" src="https://github.com/vjkr/Building_RISC-V_CPU_Core/assets/16399079/bb628f9d-e804-481f-af3f-50819e5a6d0a">
\Lot of testing is required. I will keep it for future work
tHIS IS Overall a great experience with RISC-V!!\