The RISC AR5 is a processor designed by Nayda Santiago, taking the ideas from the Simple Risc Processor, from the Jordan and Heuring textbook, a processor designed by Manuel Jimenez, Sunil Vaidya, Bradley Vansant, and Dave Dorner for the EE 813 graduate course at Michigan State University, and the processor designed by Adem Kader and Mustafa Paksoy for the E25 : COMPUTER ARCHITECTURE course at Swathmore University.
- 8-bit internal data bus
- Internal 256-word 8 bit wide program memory
- 8 byte register file
- On chip 4 bits hardware multiplier providing 8 bit results.
- 2 external I/O pins
- RISC instruction set: 18 instructions
- 3 arithmetic
- 4 logical
- 5 data transfer
- 5 control flow instructions
- 1 machine instruction
For the complete report and specifications: Simulator Report
- Victor J. Reventos Rosario
- Johanna Rivera
- Samuel Matos