VINISHA's starred repositories
SystemVerilogReference
training labs and examples
UVMReference
Reference examples and short projects using UVM Methodology
LMS-sound-filtering-by-Verilog
LMS sound filtering by Verilog
AdaptiveFilter-LMS-Verilog
Class Project - Digital Signal Processing
musical-bell-vhdl
Desenvolvimento de uma campainha musical que tocará uma música selecionada e programada na FPGA em VHDL.
Image-Processing
Image Processing Toolbox in Verilog using Basys3 FPGA
AdaptiveFilterandActiveNoiseCancellation
Adaptive Filter and Active Noise Cancellation —— LMS, NLMS, RLS
EE599_YihaoWang_7410178057
EE599 Accelerated Computing on FPGA
python-2s-complement-converter
A dec-bin converter uses 2's complement.
Design-and-implementation-of-the-low-pass-digital-filter
- Implemented 6th order low-pass digital filter for a speech signal sampled at 44KHz in Matlab FDA tool. - Created quantized RTL(second order filter instanciated thrice) in Verilog with the coefficients represented with 12 bits and maintained SNR of 36.89. - Analyzed the correlation of the Verilog implementation against the Matlab filter implementation by a self-checking script that compared the output of the Verilog implementation versus the Matlab output of the quantized filter and found the error to be 0%.
Digital-Design
Verilog HDL files
MSU-ECE-DSD
A course repository for ECE 4743/6743 – Digital Systems Design
StopWatch-Basys3
Stopwatch ⏱️ implemented using Verilog with Vivado
gilbert_cell_mixer
A gilbert cell mixer circuit implementation in LTSpice
Gilbert-Cell
Designed a Gilbert Cell in TSMC 0.18u process node. The Gilbert Cell is used for multiplication, modulation and phase detection.
timetoexplore
Source code to accompany https://timetoexplore.net
MNIST_FPGA
3 layern artificial ANN to recognize handwritten digits and implement in FPGA
Paper-with-Code-of-Wireless-communication-Based-on-DL
无线与深度学习结合的论文代码整理/Paper-with-Code-of-Wireless-communication-Based-on-DL
verilog-neural-network
Verilog implementation of a pre-trained handwritten digit recognition simple neural network.
Convolutional-Neural-Network
Implementation of CNN using Verilog
FPGA_Handwritten_digit_recognition
A Verilog implementation of a hand-written digit recognition Neural Network
jpeg-image-compression
This project has 2 parts. (1) JPEG image compression is been implemented into Matlab and (2) Verilog language using Xilinx software.
Physical-Design-with-OpenLANE-using-SKY130-PDK
This project is done in the course of "Advanced Physical Design using OpenLANE/Sky130" workshop by VLSI System Design Corporation. In this project, a PicoRV32a SoC is taken and then the RTL to GDSII Flow is implemented with Openlane using Skywater130nm PDK. Custom-designed standard cells with Sky130 PDK are also used in the flow. Timing Optimisations are carried out. Slack violations are removed. DRC is verified
VLSI-Design-Digital-System
This is this VLSI designing Project. This Project is created in Cadence Virtuoso. See the PDF for Pre-Post layout results and other details
Image-Classification-using-CNN-on-FPGA
Project is about designing a Trained Neural Network on FPGA to classify an Image Input using CNN.