vijaybharath99's repositories
32-bit-RISC-processor-with-thermal-management-unit-and-flexible-5-stage-pipelining.
The verilog code for MIPS based 32 bit RISC processor with thermal management unit and flexible 5 stage pipelining is implemented.
Language:Verilog000
IEEE-754-Floating-Point-Adder-Subtractor
This is the HDL code of IEEE 754 Floating Point Adder Subtractor in verilog.
Language:Verilog000
Karnaugh-Map
Karnaugh-map for 2 , 3 and 4 variables in both sum of product and product of sum expressions, which takes min-terms or max-terms as input and return simplified expression with desired variables.
voice-based-handcricket-like-game
A voice based (speech to speech) hand cricket like game in python