vijayan's repositories
Verilog_RTL
RTL Design using Verilog Hardware Description Language
AES128_GFMPW0
AES128 design submission for GF180 MPW0 Shuttle
caravel-gf180mcu
This repository is the GF180MCU port of Caravel. For more information about Caravel, see the original repo at https://github.com/efabless/caravel.
DAC-2020-Tutorial
Material for OpenROAD Tutorial at DAC 2020
DSP_DAC_GFMPW0
DSP Processor for GF180 MPW shuttle
graphics_controller_resubmit
MPW7 resubmission
open_pdks
PDK installer for open-source EDA tools and toolchains. Distributed with a setup for the Google/SkyWater 130nm process.
OpenLane
OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen, Fault and custom methodology scripts for design exploration and optimization.
magic-inverter
an inverter drawn in magic with makefile to simulate
OpenRAM
An open-source static random access memory (SRAM) compiler.
tt04-arbiterpuf
Submission template for Tiny Tapeout 04
vijayank88
Config files for my GitHub profile.