vignesh-raghavan

RV's repositories

Hardware Accelerator for AES 128-bit Encryption and Decryption implemented (in Verilog) in Altera's FPGA board.

Language:Verilog11 10

32-bit CRC Hardware Accelerator and Custom Instructions implemented (in Verilog) in Altera's FPGA board.

Language:C7 10

ECE 695 Course at Purdue (CUDA)

Language:C++100

ECE 563 Course at PURDUE.

Language:C000

Language:C++000

The SAT solver checks if the given CNF formula evaluates to true for some arbitrary input combinations.

Language:C++000