victorkliu's repositories
aes
Verilog implementation of the symmetric block cipher AES (Advanced Encryption Standard) as specified in NIST FIPS 197. This implementation supports 128 and 256 bit keys.
Language:VerilogBSD-2-Clause000
common_cells
Common SV components
Language:SystemVerilogNOASSERTION000
core-v-verif
Functional verification project for the CORE-V family of RISC-V cores.
Language:AssemblyNOASSERTION000
Cores-SweRV
SweRV EH1 core
Language:SystemVerilogApache-2.0000
Cores-SweRV-EL2
SweRV EL2 Core
Language:SystemVerilogApache-2.0000
cv32e40p
CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform
Language:SystemVerilogNOASSERTION000
flexfloat
C library for the emulation of reduced-precision floating point types
Language:CApache-2.0000
fpnew
Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.
Language:SystemVerilogNOASSERTION000
fpu_div_sqrt_mvp
[UNRELEASED] FP div/sqrt unit for transprecision
Language:SystemVerilogNOASSERTION000
riscv-dv
SV/UVM based instruction generator for RISC-V processor verification
Language:SystemVerilogApache-2.0000
riscv-openocd
Fork of OpenOCD that has RISC-V support
GPL-2.0000