vedadux / AES_masked_BRAM

Designs of first-order SCA-secure hardware implementations of AES encryption/decryptoin dedicated to Xilinx FPGAs (using BRAM)

AES_masked_BRAM

This repository contains the source code (HDL files) of various masked AES Encryption/Decryption function for the paper "New First-Order Secure AES Performance Records".

Licensing

Copyright (c) 2021, Aein Rezaei Shahmirzadi, Amir Moradi All rights reserved.

Please see LICENSE for further license instructions.

Publications

A. Rezaei Shahmirzadi, D. Božilov, A. Moradi (2021): "New First-Order Secure AES Performance Records" at IACR Transactions on Cryptographic Hardware and Embeded Systems 2021(2)