usman1515

SystemVerilog-for-Design-and-Verification

100DaysOfRTL

MacOS_Setup

How I setup my MacBook Air M1

caravel_huffman_encoder_decoder

Caravel user project incorporating a Huffman encoder and decoder for the GFMPW-1 open MPW Shuttle.

Designing_a_CPU_in_VHDL

dotfiles

A collection of configs for the various tools that I use. All the good stuff.

Fedora_Setup

How I setup my desktop using Fedora Workstation.

Matrix-Multiplier

OpenTCAM

An open-source Ternary Content Addressable Memory (TCAM) compiler.

Trigonometric-Function-Calculator-in-Double-FPU

usman1515

UVM_Testbench_ALU

Verilog-Language-and-Applications

FPGA_Basys3_ALU

Design, testing, synthesis and implementation of a 4-bit sequential ALU on a FPGA board.

nexysA7_fpu

sorting_network_generator

Python VHDL-generator scripts for building Odd Even Merge Sort sorting networks.

tt05_my_design

usman1515.github.io

personal webpage (Resume / CV)

UVM_Testbench_YAPP_Packet_Router

vivado_flow_navigator_scripts

Vivado Tcl scripts for simulating RTL analysis to Implementation phases in batch mode