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Location:Portland, OR
Home Page:http://umenthum.name
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A RISC-V system simulator with VGA, UART, memory, and JTAG debugging, interconnected with SystemC/TLM, designed with operating systems and computer architecture classroom use in mind.
RISC-V Debug Support for our PULP Cores
Common SV components
TCP/IP controlled VPI JTAG Interface.
LiteX IP for AX.25 packet radio
My Spin Class!!
Core SystemC Library
A simple, basic, formally verified UART controller
