ultinate / learning-vhdl

Monitoring progress in learning VHDL

VHDL Learning

This repo collects test projects of VHDL/FPGA learning process. For more details about work done, check WORKLOG.rst.

Covered so far

• Very basic FPGA Design in VHDL with multiple components
• Compile in Altera Quartus II
• Execute on FPGA testboard with Cyclone II

Work in progress

• Testbench
• RTL Simulation using ModelSim

Documentation and useful links

• IEEE Standard VHDL Language Reference Manual, 1076-2000 http://edg.uchicago.edu/~tang/VHDLref.pdf
• Altera Training http://www.altera.com/customertraining/webex/VHDL/launcher.html
• Altera Desing Examples http://www.altera.com/support/examples/vhdl/vhdl.html
• Other Tutorials http://www.seas.upenn.edu/~ese171/