Udi Finkelstein's repositories
BusPirate5-docs-firmware
Bus Pirate 5 Firmware Documentation
cycles_johnson_meyer
find all circuits of a directed graph using johnson's algorithm and java implementation by frank meyer
directed_graph_playground
An Android GUI front end to various Graph Theory algorithms
gwbackupy2sqlite
Create an SQLite metadata database from an existing gwbackupy gmail backup for browsing using datasette
inverseCSG
inversecsg code from paper https://dl.acm.org/citation.cfm?id=3275006 adapted to generate node-occ-csg-editor code
libretrack
Private, cross-platform package tracking app
LibXSVF-ESP
ESP32/8266 Arduino as (X)SVF JTAG programmer
openjscad-objects-V2
Objects created using JSCAD v2
openscad-step-reader
Proof-of-concept for OpenSCAD step file importing
PeakRDL-pdf
Converts the SystemRDL data into pdf Register specification
PeakRDL-regblock
Generate SystemVerilog RTL that implements a register block from compiled SystemRDL input.
Simple-Dialer
A handy phone call manager with phonebook, number blocking and multi-SIM support
slang
SystemVerilog compiler and language services
Surelog
SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST API. Compiles on Linux gcc, Windows msys2-gcc & msvc, OsX
systemrdl-compiler
SystemRDL 2.0 language compiler front-end
TraditionalT9
T9 English IME input for Android using hardware keypad. (e.g. SoftBank 007SH)
verilog-vcd-parser
A parser for Value Change Dump (VCD) files as specified in the IEEE System Verilog 1800-2012 standard.
VGAstarter_DE10_lite
Starter Verilog project for VGA games on DE10 lite
webexec
WebRTC server for executing command over pseudo tty and piping it’s stdin & out over data channels
YAPP_Box
Yet Another Parametric Projectbox Box