This repository contains the answers to logic layout problems with Digital and VHDL code for each class in the semester of the Digital Logic Lab (數位邏輯實習) course, held by Associate Professor Chao-Cheng Wu for first year student in Department of Electrical Engineering, National Taipei University of Technology.
To use this repository, simply download or clone this repository, and you will need the followings:
Each folder represents one class (one week). The materials.rar contains the slides used during class (Not Open Access).