Strange Cycle Count Differences

[Philipp van Kempen]

I recently added a corstone300 target based on the ARM Cortex-M55 FVP. (See #3)

While it was expected that RISCV and ARM targets arch not comparable in terms of cycle counts as they model different architectures. However as all of them should be ISS with a constant CPI of 1 I would not have expected the following:

The estimated cycles counts for the corstone300 on the same target_software tend to be 5-10 times smaller than the RISCV ones, even without features such as cmsisnn.

I can not tell if this is just the simulators being implemented very differently or if there is another issue with either the cycle count reading (e.g. Cyclce Count register overflowing at 32 bit) or different compiler optimiation flags?

[Rafael Stahl]

The largest impact could be auto vectorization applied by the compiler. (~4x or even 8x?)

The rest might be general compiler differences in terms of number of instructions executed.