tuliopereirab

arithmetic-encoder-av1

This project is being developed as part of a Master's degree research sponsored by Brazil's CNPQ. It's goal is to design a hardware architecture to accelerate the AV1 arithmetic encoder.

new_pythonProcessor

Development of a processor, in VHDL, able to executes Python Algorithm.

pamPy

Development of a processor, in Verilog, able to executes Python algorithm.

pyConv

Converter algorithm created to generate the memory inicialization files (.mif and .mem) for Quartus II and Modelsim based on Python Assembler code entry.

data-science-airport-hub

Implementacao_APA

Neander_Verilog

Hypothetical processor called Neander described using Verilog just for practice.

pythonProcessor

Carrinho_Micros

Projeto_Redes

FTP server implemented in C based on RFC 679.

Controlador_Estacionamento

Arduino project created to control a parking lot.

Monografia_TCC

Undergraduate project written in LaTeX.