trayres

PUFF

PUFF RF Circuit Design Software - Updating Pascal Code For Multi-Platform Usage

breccia-hdl

A conglomerate of sharp HDL cemented together with a replicable, scripted build flow.

edalize

An abstraction library for interfacing EDA tools

fusesoc

Package manager and build abstraction tool for FPGA/ASIC development

godot-demos

Dozens of free and open source demos for the Godot game engine

hugo-vitae

Vitae is a blog theme for Hugo that focuses on your content.

LaTeX_Git

Git Push #1

learning_nix

logisim-evolution-examples

matlab_zonst

Understanding the FFT, 2e, Zonst - Only in Matlab (rather than GWBASIC)

mechanical_keyboard_mk0

A first attempt at a mechanical keyboard.

vivado_mode

Major mode for editing Xilinx Design Constraint file (XDC) and Vivado Tcl scripts in Emacs

mechanical_keyboard_mk1

melpa

Recipes and build machinery for the biggest Emacs package repo

monorepo

A monorepo for random small projects that may be moved to other things if they merit it.

nixvim-config

Starting from the nixvim flake to try to make my OWN config!

pharo_wip

Various bits of Pharo (Smalltalk) code

pydiff

A simple GUI for python's difflib to compare files and directories

qb64_zonst

Code for "Understanding the FFT" by Anders E. Zonst, 2E, that I'm attempting to run in QB64!

retrocompute_mk0

sdl2_lazyfoo

Learning SDL2 with Lazyfoo tutorials

synlig-nix-build-test

A test of building Synlig with debug options using Nix. UHDM with debug options is imported.

trayres.github.io

Github Pages Site

TREAD

A Freepascal Schematic Capture System

TREAD_mk2

A FreePascal FSM (Finite State Machine) Editor with VHDL Output

tread_tk

Prototype FSM generator/Graphviz viewer using Python's Tk

uhdm-nix-build-test

A debug build of UHDM done with Nix. Purpose is to learn how to build all items in Synlig in debug mode and tie them all together.

verilog-ethernet

Verilog Ethernet components for FPGA implementation