Todd Strader (toddstrader)

toddstrader

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verilator

Todd Strader's repositories

verilator-dev

Verilator development

Language:C++License:LGPL-3.0Stargazers:6Issues:0Issues:0

ac-remote

Wireless controller for Fujitsu Halcyon AC units

Language:PythonLicense:GPL-3.0Stargazers:0Issues:1Issues:0

cocotb

Coroutine Co-simulation Test Bench

Language:PythonLicense:NOASSERTIONStargazers:0Issues:0Issues:0

cocotb-bus

Pre-packaged testbenching tools and reusable bus interfaces for cocotb

Language:PythonLicense:NOASSERTIONStargazers:0Issues:0Issues:0
Language:PythonLicense:NOASSERTIONStargazers:0Issues:1Issues:0

Cores-SweRV

SweRV EH1 core

Language:SystemVerilogLicense:Apache-2.0Stargazers:0Issues:2Issues:0

deep-learning

Repo for the Deep Learning Nanodegree Foundations program.

Language:Jupyter NotebookLicense:MITStargazers:0Issues:1Issues:0

verilator_ext_tests

Extended and external tests for Verilator testing

Language:SystemVerilogLicense:LGPL-3.0Stargazers:0Issues:2Issues:0
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dotfiles

Just some dotfiles

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dpi-compile

DPI protected Verilog proof of concept

Language:SystemVerilogLicense:MITStargazers:0Issues:3Issues:0

iverilog

Icarus Verilog

Language:C++License:LGPL-2.1Stargazers:0Issues:2Issues:0

ivtest

Regression test suite for Icarus Verilog.

Language:VerilogLicense:GPL-2.0Stargazers:0Issues:1Issues:0

slang

SystemVerilog compiler and language services

Language:C++License:MITStargazers:0Issues:1Issues:0

sv-tests

Test suite designed to check compliance with the SystemVerilog standard.

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test

test

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verilator

Verilator open-source SystemVerilog simulator and lint system

License:LGPL-3.0Stargazers:0Issues:0Issues:0

verilator-enum-func

Verilator has problems with constant functions that return enums

Language:C++License:LGPL-3.0Stargazers:0Issues:1Issues:0

verilator-integer-array

Can't typedef an integer array

Language:C++License:LGPL-3.0Stargazers:0Issues:1Issues:0

verilator-intf-err-msg

Totally unhelpful interface error message

License:LGPL-3.0Stargazers:0Issues:2Issues:0
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verilator-long-module-name

Regression test for long module names in Verilator

Language:C++License:LGPL-3.0Stargazers:0Issues:2Issues:0

verilator-scope-map

Adding a scope map to the symbol table class for more design reflection

Language:C++License:LGPL-3.0Stargazers:0Issues:1Issues:0

verilator-setbit-fix

Fixing V3Number::setBit()

Language:C++License:LGPL-3.0Stargazers:0Issues:1Issues:0

verilator-static-elab

Hacking on things that should be const-able

Language:C++License:LGPL-3.0Stargazers:0Issues:1Issues:0

vimium

The hacker's browser.

License:MITStargazers:0Issues:0Issues:0

wbuart32

A simple, basic, formally verified UART controller

Language:VerilogLicense:GPL-3.0Stargazers:0Issues:0Issues:0