tjupathfinder

e200_opensource

The Ultra-Low Power RISC Core

awesome-ISP

A curated list of awesome ISP frameworks, papers, libraries, resources, and shiny things.

NyuziProcessor

GPGPU microprocessor architecture

gen_apb_file

async_fifo

A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog

YASA

:snail:Yet Another Simulation Architecture

OpenSoCFabric

OpenSoC Fabric - A Network-On-Chip Generator

darkriscv

opensouce RISC-V implemented from scratch in one night!

SuperScalar-RISCV-CPU

SSRV(Super-Scalar RISC-V) --- Super-scalar out-of-order RV32IMC CPU core, 6.0 CoreMark/MHz.

chisel-book

Digital Design with Chisel

riscv

RISC-V CPU Core (RV32IM)

systemctlm-cosim-demo

riscv-elf-psabi-doc

A RISC-V ELF psABI Document

Open_RegModel

:hatched_chick:Use ORDT and systemRDL tools to generate C/Verilog header files, register RTL, UVM register models, and docs from compiled SystemRDL.

mips-cpu

MIPS CPU implemented in Verilog