three-bee / 16-bit-CPU

Custom 16-bit ISA with multi-cycle CPU, written in Verilog

16-bit-CPU

Custom 16-bit ISA with multi-cycle CPU, written in Verilog.

Covers the last two lab experiments of Middle East Technical University, Electrical and Electronics Engineering Department, EE446 Computer Architecture 2 course.

General Information

• Suitable hardware for this ISA contains:
  • Von-Neumann architecture memory of 64 words, each word is of W=8 bits (byte-addressable memory). 6 of 8 bits are required for addressing the memory.
  • 8 general purpose registers of size 8 bits. 3 of 8 bits are required for addressing the registers.
  • PC (R7) and LR (R6) of size 8 bits are inside the general-purpose registers.

Addresses	Content
0x22	0xC4	Some data
..
..	0xB2	Instruction #1
0x02	0x01
0x01	0x03	Instruction #0
0x00	0x71

Opcodes

Examples are given in ARM mnemonic.

OP = 00 (Arithmetic operations)

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OP		CMD		I	Rd
00		CMD		0	Rd			Rn			x	x	Rm
00		CMD		1	Rd			rot			imm5

CMD	function	pseudo instructions	examples
00	ADD	Rd <-- Rn CMD Rm if I = 0 Rd <-- Rd CMD (extimm5 ROL rot) if I = 1	CMD R5,R3,R0 CMD R4,#20 (imm5=20, rot=0) CMD R2,#80 (imm5=20, rot=2)
01	SUB
10	CMP	X <-- Rn SUB Rm if I = 0 X <-- Rd SUB (extimm5 ROL rot) if I = 1
11	MOV	Rd <-- (extimm5 ROL rot) and I = 1

OP = 01 (Logic operations and shifting)

• 3-bit shamt (0-7) can move the extended 5-bit immediate value to all possible locations in the 8-bit register. ROR is handled by ROL (ROR(x)=ROL(8-x)).

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OP		CMD			Rd
01		CMD			Rd			Rn			x	x	Rm
01		CMD			Rd			rot			imm5

CMD	function	pseudo instructions	examples
000	ADD	Rd <-- Rn CMD Rm	AND R5,R3,R0 LSL R4,#2 (rot=x, imm5=2) ROL R3,#6 ROR R3,#2 (imm5=8-2=6)
001	OR
010	XOR
011	ROL	Rd <-- Rd CMD extimm5
100	ROR
101	LSL
110	LSR
111	ASR

OP = 10 (Memory operations)

• H determines which half of the memory to be addressed. Normally, addr/offset should allocate 6 bits. However, to keep the bit positions of Rn and Rd in the same place for all instruction types, immediate value is considered to have 5 bits. The most significant bit is H, being the 6th bit.
• H is handled in the extender module.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OP		L	I	H	Rd			Rn			addr5/offset5

L	function	pseudo instructions	examples
1	LDR	Rd <-- MEM[Rn + {H, offset5}] if I = 0 Rd <-- MEM[{H, addr5}] if I = 1	LDR R0, [R1,#3] LDR R0,#63 (offset5=31, H=1) STR R1, [R0] STR R0,#2
0	STR	Rd --> MEM[Rn + {H, offset5}] if I = 0 Rd --> MEM[{H, addr5}] if I = 1

OP = 11 (Branching)

• Each instruction is 2 bytes. The memory is byte addressable. Due to the architecture's 3-stage pipeline, branch target address is laoded to PC + 2 instructions ahead = PC + 2.
• Rd=R6 needs to be set for BL, hence INSR[10:8] = 110.

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
OP		type		flag		x	x	x	x	addr6
01		x0		xx		x	x	x	x	addr6
01		01		x	1	1	0	x	x	addr6

type	flag	function	explanation	pseudo instructions
00	x	B	branch	PC + 2 <-- addr6
01	x	BL	branch with link	LR(R6) <-- PC PC + 2 <-- addr6
10	x	BI	branch indirect	PC + 2 <-- MEM[addr6]
11	00	BEQ	branch if zero	B if condition satisfied
11	01	BNE	branch if not zero
11	10	BHS/BCS	branch if carry
11	11	BLO/BCC	branch if not carry

Datapath

• As the baseline, Harris & Harris' multicycle ARM datapath design is taken and modified extensively.
• For more details and the datapath architecture, please refer to the project report.

Controller

• A finite state machine in Verilog is written for the controller. Minimum number of states is not seeked, hence the available states can be reduced.
• For more details and the state diagram, please refer to the project report.

Example programs

• Please refer to the project report and memory file in the repository.