tgingold

OpenTDC

Time to Digital Converter (TDC)

caravel_OpenTDC

Caravel is a standard SoC hardness with on chip resources to control and read/write operations from a user-dedicated space.

a2i

mhdlsim

OSVVM

Open Source VHDL Verification Methodology (OSVVM) Repository

vunit

VUnit is a unit testing framework for VHDL/SystemVerilog

cocotb

Coroutine Co-simulation Test Bench

docker

Scripts to build and use docker images including GHDL

ghdl_debian

Workplace for GHDL Debian package

gtkwave

GTKWave is a fully featured GTK+ based wave viewer for Unix and Win32 which reads LXT, LXT2, VZT, FST, and GHW files as well as standard Verilog VCD/EVCD files and allows their viewing.

microwatt

A tiny Open POWER ISA softcore written in VHDL 2008

miniradius

open_mpw_precheck

open_pdks

PDK installer for open-source EDA tools and toolchains. Distributed with a setup for the Google/SkyWater 130nm process.

openlane

OpenLANE is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen, Fault and custom methodology scripts for design exploration and optimization.

OpenROAD

OpenROAD's unified application implementing an RTL-to-GDS Flow

OpenSTA

OpenSTA engine