testpink's starred repositories
512-Bit-SRAM
Design of 512-Bit SRAM using four 128bits banks using Cadence Virtuoso
SRAM-Design
This repository displays pictorial representation of a 512-bit SRAM Design. The SRAM design is completed with four 128-bit banks. The schematic and the layout are constructed with the help of Cadence Virtuoso.
VLSI_LowPower_SRAM
Final Electrical Engineering Capstone Project: Research and Design of Low Power SRAM using Cadence Virtuoso
256-bit-SRAM
256 BIT SRAM Memory System Design using 6T cell to store the bits using 45nm technology on Cadence
16x4-6T-SRAM-Memory-Block
Layout of 64 bit SRAM Memory Block using Cadence Virtuoso.
A-VLSI-SRAM-8x2-Array-in-Cadence-Virtuoso
VLSI Design of an 8 x 2 SRAM Array | Cadence Virtuoso
Layout-Design-of-an-8x8-SRAM-array
The project is about building an 8-row by 8-bit 6T SRAM memory array, & a 3-to-8 decoder that's used to access the SRAM array. The layout design is done using Cadence Virtuoso’s ADE, & the Static Noise Margin is obtained through Matlab scripts.
Modica-SRAM
Design of a 32-kbit synchronous SRAM with 32-bit words, using 180 nm process technology. Developed MATLAB scripts to evaluate architectural trade-offs between performance (using logical effort analysis) and area usage; see the source code for the HSPICE decks and MATLAB scripts that are used during architectural trade-off evaluation, and characterization of inverters for different supply voltages (VDD) and temperatures. It also includes HSPICE decks for the characterization of the 6-transistor SRAM cell for different transistor ratios, and the SRAM read and write circuitry. Co-designed and co-developed the SRAM using schematic entry in Cadence Virtuoso. Performed functional and timing verification by simulating extracted SPICE netlist in NanoSim.