Programmer tool for Lattice iCE5 (iCE40 Ultra) FPGA
USB Custom HID interface. FPGA bitstream is uploaded to FPGA SRAM!
Supported hardware
- STM32F3Discovery
Pinout:
| Pin | Func |
|---|---|
| PA5 | SCK |
| PA7 | MOSI |
| PB0 | CS |
| PB1 | CRST |
| PB2 | CDONE |
| PE8 | LED |
Pinout:
| Pin | Func |
|---|---|
| PA5 | SCK |
| PA7 | MOSI |
| PB0 | CS |
| PB1 | CRST |
| PB2 | CDONE |
| PA9 | LED |
Loading algo for iCE40
- CS set low.
- CRST set low.
- Wait CDONE goes low.
- CRST set high.
- Wait some time (FPGA loading).
- Send bitstream via SPI (8 bits MSP, Mode=0), ~70 kbytes, 80 bytes header included.
- Periodically send 0xFF and wait CDONE goes high.
- After CDONE goes high send 49 clock pulses (7 bytes) and set CS high.