Nasreddine Tebina's repositories
blif2verilog
Simple blif to verilog converter in C++
chipwhisperer
ChipWhisperer - the complete open-source toolchain for side-channel power analysis and glitching attacks
Language:VHDLNOASSERTION000
Language:VerilogMIT000
Fortuna-CSPRNG
Hardware implementation of the Fortuna PRNG algorithm
Language:VerilogMIT000
iacrtrans
LaTeX class for the IACR Transactions on Symmetric Cryptology
Language:PostScriptCC0-1.0000
my-dotfiles
My tmux and neovim config
OpenLane
OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.
Language:VerilogApache-2.0000
OPTEE-OS-Build
OPTEE OS build makefiles
Language:BitBake000
Parser-SPEF
A Fast C++ Header-only Parser for Standard Parasitic Exchange Format (SPEF).
Language:C++MIT000
Ray-Spect
A tool to insert parametric modifications into a specter netlist
Language:PythonMIT000
Language:SystemVerilogMIT000
Language:Python000
wb2axip
Bus bridges and other odds and ends
Language:Verilog000