taylor-bsg's repositories
clusterv-soc
Quad cluster of RISC-V cores with peripherals and local memory
eFPGA---RTL-to-GDS-with-SKY130
This repo shows an implementation of an FPGA from RTL to GDS with open Skywater-130 pdk
hb-pytorch
Repo to hold HammerBlade PyTorch port. Based on PyTorch v1.4.0
MM
Miner Manager
NeuriCam
Deep learning based video sensing method for low-power IoT cameras (Smart glasses, GoPro, Blink etc.).
ODSA-BoW
Repo for all activity related to the ODSA Bunch of Wires Specification
onnxruntime-riscv
Fork of upstream onnxruntime focused on supporting risc-v accelerators
openc906
OpenXuantie - OpenC906 Core
openc910
OpenXuantie - OpenC910 Core
opene902
OpenXuantie - OpenE902 Core
opene906
OpenXuantie - OpenE906 Core
OpenSTA
OpenSTA engine
pono
Next generation cosa.
sky130-hello-world
Minimal SKY130 example with self-checking LVS, DRC, and PEX
tt02-verilog-demo
Verilog demo for TT02
vivado-risc-v
Xilinx Vivado block designs for FPGA RISC-V SoC running Debian Linux distro
wav-build
Repository with infrastructure required to build Wavious Software
wav-lpddr-hw
Wavious DDR (WDDR) Physical interface (PHY) Hardware
wav-lpddr-sw
Wavious DDR (WDDR) Physical interface (PHY) Software
wav-rtos-sw
Wavious RTOS Base Software
xchange
Change part number or package in a Xilinx 7-series FPGA bitstream
XiangShan
Open-source high-performance RISC-V processor
xls
XLS: Accelerated HW Synthesis
xuantie-gnu-toolchain
GNU toolchain for Xuantie RISC-V CPU, including GCC and Binutils ……