CS 256: Simple Processor Design Project
Made by: Tarun Gupta (180001059) and Kartik Garg (180002027).
Clock period is 10 ns. The inputs A and B are available for ONLY 1st clock-cycle, during which they are stored in 8 bit registers. After the 1st clock-cycle, the inputs are not available (made 0s).
Description of Files:
Adder: 8 bit full adder.
FA: 1 bit full adder.
Subtractor: 8 bit full subtractor.
Sub: 1 bit full subtractor.
Decoder: takes in 3 bit input, and outputs 8 bit output.
ALU_VHDL: Implementation of ALU.
PIPO_register_8: Implemntation of Parallel In, Parallel Out 8-bit register.
UP_counter: Implementation of 3-bit synchronous upcounter.
Control_Unit: Control Unit.
A_part: Part A of 1st Problem set.
B_part: Part B of 1st Problem set.
C_part: Part C of 1st Problem set.
D_part: Part D of 1st Problem set.
E_part: Part E of 1st Problem set.
F_part: Part F of 1st Problem set.
G_part: Part G of 1st Problem set.
H_part: Part H of 1st Problem set.