wong_hs's repositories
5G-NR-Planning-And-Dimensioning
Planning and Dimensioning for 5G NR Radio
core_ddr3_controller
A DDR3 memory controller in Verilog for various FPGAs
ldpc-3gpp-matlab
Matlab simulations of the encoder and decoder for the New Radio LDPC code from 3GPP Release 15
Practical-UVM-Step-By-Step
This is the main repository for all the examples for the book Practical UVM
abu
阿布量化交易系统(股票，期权，期货，比特币，机器学习) 基于python的开源量化交易，量化投资架构
awesome-5g
Awesome lists about 5G projects.
core-v-verif
Functional verification project for the CORE-V family of RISC-V cores.
Deep-Learning-with-TensorFlow-book
深度学习入门开源书，基于TensorFlow 2.0案例实战。Open source Deep Learning book, based on TensorFlow 2.0 framework.
eat_tensorflow2_in_30_days
Tensorflow2.0 🍎🍊 is delicious, just eat it! 😋😋
fucking-algorithm
刷算法全靠套路，认准 labuladong 就够了！English version supported! Crack LeetCode, not only how, but also why.
Go
Algorithms Implemented in GoLang
hdl
HDL libraries and projects
LM-RISCV-DV
An Open Source Design Verification Environment for RISC-V
MPSoC-DV
MPSoC verified with UVM/OSVVM/FV
NandFlashController
AXI Interface Nand Flash Controller (Sync mode)
new-pac
科学上网/自由上网/翻墙/软件/方法，一键翻墙浏览器，免费shadowsocks/ss/ssr/v2ray/goflyway账号/节点分享，vps一键搭建脚本/教程
NyuziProcessor
GPGPU microprocessor architecture
openISP
Image Signal Processor
openwifi
open-source IEEE802.11/Wi-Fi baseband chip/FPGA design
openwifi-hw
FPGA/hardware design of openwifi
QCSuper
QCSuper is a tool communicating with Qualcomm-based phones and modems, allowing to capture raw 2G/3G/4G radio frames, among other things.
srsLTE
Open source SDR LTE software suite from Software Radio Systems (SRS)
tnoc
Network on Chip Implementation written in SytemVerilog
UERANSIM
Open source 5G UE and RAN (gNodeB) simulator
Vitis-AI
Vitis AI is Xilinx’s development stack for AI inference on Xilinx hardware platforms, including both edge devices and Alveo cards.
yuu_register_productor
UVM register utility generation by inputting xls table