takeshineshiro / iDMA

A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)

iDMA

Home of the iDMA - a modular, parametrizable, and highly flexible Data Movement Accelerator (DMA) architecture targeting a wide range of platforms from ultra-low power edge nodes to high-performance computing systems. iDMA is part of the PULP (Parallel Ultra-Low-Power) platform, where it is used as a cluster level DMA in the Snitch Cluster and in the PULP Cluster.

iDMA currently implements the following protocols:

• AXI4+ATOPs from AXI5
• AXI4 Lite
• OBI v1.5.0

Modular Architecture

iDMA is centered around the idea to split the DMA engine in 3 distinct parts:

• Frontend: The frontend implements the communication with the platform and emits transfer requests
• Midend: Midend(s) transform a transfer request from the frontend to generic 1D transfers, which can be handled by the backend.
• Bakend: The backend gets a 1D transfer (src_addr, dst_addr, length) and executes it on the transport protocol's manager interface.

The interface between the parts are well-defined, making it easy to adapt to a new system or to add new capabilities.

Documentation

The latest documentation can be accessed pre-built. The Morty docs provide the generated description of the SystemVerilog files within this repository.

License

iDMA is released under Solderpad v0.51 (SHL-0.51) see LICENSE:

Contributing

We are happy to accept pull requests and issues from any contributors. See CONTRIBUTING.md for additional information.

Getting Started

Prerequisites

iDMA can directly be integrated after cloning it from this repository. However, to regenerate the configuration registers, build the documentation, and run various checks on the source code, various tools are required.

• bender >= v0.24.0
• morty >= v0.6.0
• Verilator = v4.202
• Verible >= v0.0-1051-gd4cd328
• Python3 >= 3.8 including some the libraries listed in requirements.txt

Building the Documentation

Use make doc to build the documentation. The output is located at doc/build.

Simulation

We currently do not include any free and open-source simulation setup. However, if you have access to Questa advanced simulator, a simulation can be launched using:

make prepare_sim
export VSIM="questa-2022.3 vsim"
$VSIM -c -do "source scripts/compile_vsim.tcl; quit"
$VSIM -c -t 1ps -voptargs=+acc \
     +job_file=jobs/backend/man_same_dst_simple.txt \
     -logfile logs/backend.simple.vsim.log \
     -wlf logs/backend.simple.wlf \
     tb_idma_obi_backend \
     -do "source scripts/start_vsim.tcl; run -all"

with gui:

$VSIM -t 1ps -voptargs=+acc \
     +job_file=jobs/backend/man_same_dst_simple.txt \
     -logfile logs/backend.simple.vsim.log \
     -wlf logs/backend.simple.wlf \
     tb_idma_obi_backend \
     -do "source scripts/start_vsim.tcl; source scripts/waves/vsim_obi_backend.do; run -all"

Where:

• +job_file=jobs/backend/man_simple.txt can point to any valid job file
• -logfile logs/backend.simple.vsim.log denotes the log file
• -wlf logs/backend.simple.wlf specifies a wave file
• tb_idma_backend can be any of the supplied testbenches (test/tb_idma_*)