processor_design
Project1 contains a 16-bit very simple computer developed for the teaching purpose. The IITB-RISC is an 8-register, 16-bit computer system. The architecture is well optimized for performance.
Project2 contains a 6 stage pipelined processor, IITB-RISC, whose instruction set architecture is provided. IITB-RISC is a 16-bit very simple computer developed for the teaching purpose. The IITB-RISC is an 8-register, 16-bit computer system. It follows the standard 6 stage pipelines (Instruction fetch, instruction decode, register read, execute, memory access, and write back).