svuvm12 / uvm_all_wr_rd

UVM register sequence to write all registers and read back with fix pattern

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uvm_all_wr_rd

UVM register sequence to write all registers and read back with fix pattern

How to use ? Use this sequence same as uvm reg bit bash sequnce . Pass register model and start sequence same as bit_bash / hw_reset sequence.

Sequence Flow

-> Write all Register in block with data as all '1 -> Read back and compare -> Write all Register in block with random data -> Read back and compare

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UVM register sequence to write all registers and read back with fix pattern

License:Apache License 2.0


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Language:SystemVerilog 100.0%