superfpga

axi

AXI4 and AXI4-Lite synthesizable modules and verification infrastructure

superemacs.d

AMBA_AXI_AHB_APB

AMBA bus lecture material

AXI4

AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream transmitter and receiver verification components

core_ddr3_controller

A DDR3 memory controller in Verilog for various FPGAs

Cores-SweRV

SweRV EH1 core

dotemacs

fpga-network-stack

Scalable Network Stack for FPGAs (TCP/IP, RoCEv2)

hdl

HDL libraries and projects

hdl_checker

Repurposing existing HDL tools to help writing better code

irig-decoder

Firmware IRIG-B decoder

jetson-rdma-picoevb

Minimal HW-based demo of GPUDirect RDMA on NVIDIA Jetson AGX Xavier running L4T

jpeg_open

A hardware MJPEG encoder and RTP transmitter

linux-xlnx

The official Linux kernel from Xilinx

oni

Oni: Modern Modal Editing - powered by Neovim

org-mind-map

This is an emacs package that creates graphviz directed graphs.

org-roam-ui

A graphical frontend for exploring your org-roam Zettelkasten

riscv

RISC-V CPU Core (RV32IM)

SD-card-controller

WISHBONE SD Card Controller IP Core

SPI

Exchange data using spi, the code simulate the master's behavior of send data to slave.

style-guides

lowRISC Style Guides

svunit

verilog-axi

Verilog AXI components for FPGA implementation

verilog-axis

Verilog AXI stream components for FPGA implementation

verilog-ethernet

Verilog Ethernet components for FPGA implementation

verilog-i2c

Verilog I2C interface for FPGA implementation

verilog-pcie

Verilog PCI express components

verilog-uart

Verilog UART

VLSI

RISC V core implementation using Verilog.

wujian100_open

IC design and development should be faster，simpler and more reliable