SUISUISI's repositories
FPGAandCNN
基于FPGA的数字识别-实时视频处理的定点卷积神经网络实现
Xilinx_Library
Vivado诸多IP,包括图像处理等
FPGAandImage
image processing based FPGA
FPGAandGames
FPGA实现各种小游戏,学习并快乐着
FPGAandUSB3.0
FPGA和USB3.0桥片实现USB3.0通信
FPGATechnologyGroup
FPGA Technology Exchange Group相关文件管理
FPGAandPeripheralInterface
Peripheral Interface of FPGA
FPGAandStudy
帮助大家进行FPGA的入门,分享FPGA相关的优秀文章,优秀项目
basic_systemverilog
Must-have verilog systemverilog modules
FPGAandLAN
FPGAandLAN
AXI4-Stream-FIR-filter
AXI4-Stream FIR filter IP
KnowledgeGraphofFPGA
Knowledge Graph of FPGA
SystemVerilog
SystemVerilog of syntax and Practices
zynq_guide
ZYNQ从放弃到入门系列资源
CameraLinkVisionKit
Vision Kit for microZED SoM
vivado-library
Digilent_vivado-library
BrainCircuit
FPGA and BrainCircuit
mist-firmware
Firmware source code for the MIST board
RetroPieBIOS
BIOS collection for RetroPie
AmmeterClock
Using an ammeter and FPGA to create a clock
Language:GLSLGPL-3.0000
hls
fpga hls IP and project
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