SUISUISI (suisuisi)

suisuisi

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SUISUISI's repositories

FPGAandCNN

基于FPGA的数字识别-实时视频处理的定点卷积神经网络实现

Xilinx_Library

Vivado诸多IP,包括图像处理等

Language:VHDLLicense:MITStargazers:140Issues:5Issues:1

FPGAandImage

image processing based FPGA

Language:VHDLLicense:GPL-3.0Stargazers:93Issues:4Issues:0

FPGAandGames

FPGA实现各种小游戏,学习并快乐着

Language:VHDLLicense:MITStargazers:54Issues:4Issues:0

FPGAandUSB3.0

FPGA和USB3.0桥片实现USB3.0通信

Language:VHDLLicense:MITStargazers:45Issues:0Issues:0

FPGATechnologyGroup

FPGA Technology Exchange Group相关文件管理

Language:VerilogStargazers:37Issues:0Issues:0

FPGAandPeripheralInterface

Peripheral Interface of FPGA

Language:VerilogStargazers:30Issues:3Issues:0

FPGAandStudy

帮助大家进行FPGA的入门,分享FPGA相关的优秀文章,优秀项目

Stargazers:29Issues:0Issues:0

gamegirl

fpga based nes box

Language:VHDLLicense:GPL-3.0Stargazers:25Issues:2Issues:0

basic_systemverilog

Must-have verilog systemverilog modules

Language:VerilogLicense:MITStargazers:22Issues:0Issues:0

FPGAandLAN

FPGAandLAN

Language:VHDLStargazers:22Issues:0Issues:0

jtag

fpga jtag hardware

License:MITStargazers:17Issues:2Issues:0

AXI4-Stream-FIR-filter

AXI4-Stream FIR filter IP

Language:VerilogStargazers:11Issues:2Issues:0

KnowledgeGraphofFPGA

Knowledge Graph of FPGA

EBAZ4205

EBAZ4205 is Xilinx Zynq based mining board used in Ebang Ebit E9+ bitcoin miner machine.

License:MITStargazers:8Issues:2Issues:0

oldcpu

Ancient CPU Revelation

Language:VerilogStargazers:6Issues:0Issues:0

SystemVerilog

SystemVerilog of syntax and Practices

Language:SystemVerilogLicense:MITStargazers:6Issues:2Issues:0

mipi-demo

MIPI CSI-2 + MIPI CCS Demo

Language:VerilogLicense:NOASSERTIONStargazers:5Issues:2Issues:0

teroshdl

teroshdl例程

Language:VerilogStargazers:5Issues:0Issues:0

zynq_guide

ZYNQ从放弃到入门系列资源

Language:CLicense:MITStargazers:5Issues:0Issues:0

CameraLinkVisionKit

Vision Kit for microZED SoM

Language:VerilogStargazers:4Issues:2Issues:0

openfpga

公众号OpenFPGA开源项目汇总

License:MITStargazers:3Issues:4Issues:0

oh

Verilog library for ASIC and FPGA designers

License:MITStargazers:2Issues:0Issues:0

vivado-library

Digilent_vivado-library

Language:CLicense:MITStargazers:2Issues:1Issues:0

BrainCircuit

FPGA and BrainCircuit

Language:StataLicense:GPL-3.0Stargazers:1Issues:3Issues:0

mist-firmware

Firmware source code for the MIST board

Language:CStargazers:1Issues:2Issues:0

myhdl

The MyHDL development repository

License:LGPL-2.1Stargazers:1Issues:0Issues:0

RetroPieBIOS

BIOS collection for RetroPie

Language:PythonStargazers:1Issues:2Issues:0

AmmeterClock

Using an ammeter and FPGA to create a clock

Language:GLSLLicense:GPL-3.0Stargazers:0Issues:0Issues:0

hls

fpga hls IP and project

Stargazers:0Issues:0Issues:0