strath-sdr / rfsoc_qpsk

PYNQ example of using the RFSoC as a QPSK transceiver.

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SysGen and iprepo HDL out of sync

cramsay opened this issue · comments

Fix in PR#1 (#1) has been applied to generated HDL only.

Can someone with SysGen access update the data inspector for the last rx "tap off"? FIFO depth should be 127, and the constant for the read threshold should be 63.

Currently, the system generator model produces a broken IP. It is being worked on.

Fixed by PR #11